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Quad, IEEE 802.3at/af PSE Controller
for Power-over-Ethernet
Status Registers (R0Ch–R11h)
Port Status Registers (R0Ch–R0Fh)
The Port Status registers (R0Ch–R0Fh, Table 13) record
the results of the port detection and classification at the
end of each phase in three encoded bits. On power-
up or after a reset condition, the Port Status register
is set to a default value of 00h. Tables 14 and 15 are
the detection and classification result decoding tables
respectively. For LEG_EN = 0 (Port GPMD register, Table
Table 13. Port Status Register
ADDRESS = 0Ch, 0Dh, 0Eh, 0Fh
SYMBOL BIT NO. TYPE
39), the detection result is shown in Table 13. When
CLC_EN = 1, the device allows valid detection of high
capacitive loads of up to 100 F F (typ), and reports the
result as HIGH_CAP. If CL5_EN_ = 1, any classification
current in excess of Class 4 but less than the classifica-
tion current limit will return a Class 5 classification result.
If CL5_EN_ = 0, any classification current in excess of
Class 4 will return a current-limit classification result, and
the port will not power up.
DESCRIPTION
Reserved
CLASS_[2:0]
Reserved
DET_ST_[2:0]
7
6
5
4
3
2
1
0
—
R
R
R
—
R
R
R
Reserved
Classification result for the corresponding port (Table 14)
Reserved
Detection result for the corresponding port (Table 13)
Table 14. Detection R esult    Decoding Char t
DET_ST_[2:0]
000
001
010
011
100
101
110
111
DETECTED
NONE
DCP
HIGH CAP
RLOW
DET_OK
RHIGH
OPEN
DCN
DESCRIPTION
Detection status unknown (default)
Positive DC supply connected at the port (V AGND - V OUT_ < 1V)
High capacitance at the port (> 8.5 F F (typ))
Low resistance at the port (R DET < 15k I )
Detection pass (15k I > R DET > 33k I )
High resistance at the port (R DET > 33k I )
Open port (I OUT_ < 10 F A)
Low impedance to V EE at the port (V OUT_ - V EE < 2V)
Table 15. Classification Result Decoding Chart
34
CLASS_[2:0]
000
001
010
011
100
101
110
111
CLASS RESULT
Unknown
1
2
3
4
5
0
Current limit
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